1. Field of the Invention
The present disclosure relates to a non-volatile logic circuit and a method for operating the nonvolatile logic circuit as an exclusive-OR (XOR) circuit.
2. Description of the Related Art
FIG. 8 to FIG. 12C are reproductions of FIG. 1 to FIG. 5 of United States Pre-Grant Patent Application Publication No. 2009/0097299 (Hereinafter, Patent Document 1), which corresponds to Japanese Laid-Open patent publication No. 2009-099606.
As shown in FIG. 8, a semiconductor memory device 10 according to Patent Document 1 includes a stacked layer of a ferroelectric layer 13 and a semiconductor layer 14. In the semiconductor memory device 10, a first electrode 12 is formed on the stacking layer at the ferroelectric layer 13 side and a plurality of second electrodes 15a, 15b and 15c are formed on the stacked layer at the semiconductor layer 14 side. These layers are formed on a substrate 1.
FIGS. 9A and 9B show an initial state of the semiconductor memory device 10. FIG. 9A is a cross-sectional perspective view and FIG. 9B is an equivalent circuit diagram.
For example, when an n-type semiconductor material is used for the semiconductor layer 14, all polarizations 16 are oriented in the same direction so that the polarizations 16 of the ferroelectric layer 13 are coupled with electrons (majority carriers) of the semiconductor layer 14 in an initial state. In this case, two-dimensional electrons 17 induced by polarization in the ferroelectric layer 13 are accumulated around an interface between the semiconductor layer 14 and the ferroelectric layer 13, and the semiconductor layer 14 is in a low resistance state. Thus, the semiconductor layer 14 serves as a channel in which a current flows in the same manner as a metal electrode and can be used as a uniform electrode as a metal electrode. In such a case, as shown in FIG. 9B, a conduction state between the semiconductor layer 14 and each of the second electrodes 15a, 15b and 15c is short-circuited.
In this state, as shown in FIG. 10A, when a bias voltage relatively high to the first electrode 12 is applied to the second electrode 15c to invert the polarization only in part of the ferroelectric layer 13 located in which the second electrode 15c is formed, the polarization 16 is oriented in a direction which causes deletion of electrons in the semiconductor layer 14. Accordingly, only the part 18 of the semiconductor layer 14 located in the region in which the second electrode 15c is formed is depleted and thus becomes in a high resistance state. As a result, as shown in FIG. 10B, a state between the semiconductor layer 14 and the second electrode 15c is an open-circuit state.
FIGS. 11A, 11B and 11C show two resistance states of part of the semiconductor layer 14 located in a region in which a second electrode 15 is formed. FIG. 11A is a cross-sectional view of the part when it is in a low resistance state, FIG. 11B is a cross-sectional view of the part when it is in a high resistance state, and FIG. 11C is a table showing sheet resistance values between the semiconductor layer 14 and the second electrode 15. As shown in the table, each of the parts 18 of the semiconductor layer 14 located in regions in which the second electrode 15 is formed can be in either of two states having different sheet resistance values because of the polarization assist effect of the ferroelectric layer 13.
In the state shown in FIG. 11B, a bias voltage relatively low to the first electrode 12 is applied to the second electrode 15 to invert again the polarization of the ferroelectric layer 13. Thus, the polarization is oriented in the direction in which electrons are accumulated and the part 18 of the semiconductor layer 14 located in the region in which the second electrode 15 is formed is back to a low resistance state. As a result, the conduction state between the semiconductor layer 14 and the second electrode 15 becomes in a short circuit state again.
FIGS. 12A, 12B and 12C show results of measurement for resistance values of the semiconductor layer 14 using a four-probe method. FIG. 12A is a diagram illustrating how the resistance value of the semiconductor layer 14 is measured when it is in a low resistance state where two-dimensional electrons are accumulated, FIG. 12B is a diagram illustrating how the resistance value of the semiconductor layer 14 is measured when it is in a high resistance state where two-dimensional electrons are depleted, and FIG. 11C is a table showing respective measurement results. As shown in the table of FIG. 11C, the resistance value of the semiconductor layer 14 is about 1×103 ohm per square or less in a low resistance state and about 1×106 ohm per square or more in a high resistance state.
The above description is cited from paragraphs [0057] and [0062]-[0067] of US Pre-Grant Patent Application Publication No. 2009/0097299, which corresponds to paragraphs [0028] and [0033]-[0038] of Japanese Laid-Open patent publication No. 2009-099606.